1. Field of the Invention
The present invention relates to integrated circuits, and, in particular, to non-volatile memory cells.
2. Description of the Related Art
A single-poly EEPROM (electronically erasable programmable read-only memory) cell structure implemented in a standard CMOS process is described by K. Ohsaki, N. Asamoto, and S. Takagaki in "A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes," IEEE Journal of Solid-State Circuits, Vol. 29, No. 3, March 1994, pp. 311-316 ("the Ohsaki paper"), the teachings of which are incorporated herein by reference.
FIGS. 1A and 1B show a schematic and a topologic view, respectively, of the single-poly EEPROM cell 100 described in the Ohsaki paper (also referred to as the IBM cell). Single-poly EEPROM cell 100 comprises a PMOS transistor MC1102 and an adjacent NMOS transistor M2104 that share an electrically isolated common polysilicon gate 106. The common gate 106 works as a floating gate with the inversion layer of the PMOS transistor and p+ diffusions working as a control gate 108.
The Ohsaki paper describes single poly EEPROM cells in the context of a 0.8-micron standard logic CMOS process. The Ohsaki paper describes two different techniques for erasing the single poly EEPROM cell: one relies on FN (Fowler Nordheim) tunneling between the floating gate 106 and the p+diffusion in the PMOS transistor 102 and the other relies on FN tunneling between the floating gate 106 and the n+ diffusion in the NMOS transistor 104. In either case, a voltage of sufficient magnitude must be applied across the oxide separating the polysilicon gate from the underlying structure in order to achieve the desired FN tunneling.
Conventional non-volatile memory cells require at least about 90-100A of oxide to separate the polysilicon gate from the underlying structure to maintain data in the cells for a reasonable time (about 10 years). To erase a cell through FN tunneling, the electric field across this tunnel oxide must be at least about 10MV/cm. Thus, to achieve FN tunneling across a 90-100A tunnel oxide, a voltage of at least about 9-10V would need to be applied across the oxide to perform an erase operation.
According to the Ohsaki paper, the erase voltage is applied to the source/drain of the devices. As such, the 9-10V erase voltage would need to be applied to the device junctions. However, in advanced deep sub-micron technologies, the junction breakdown of devices is rapidly decreasing. For example, in some 0.25-micron technologies, junction breakdown voltages are as low as 7V. Moreover, this junction breakdown voltage level will likely continue to decrease as devices are scaled down even more. As such, the single poly EEPROM cell structure described in the Ohsaki paper cannot be effectively implemented for deep sub-micron technologies of at least 0.25 .mu.m and smaller, because the voltages required to perform an erase operation would likely result in device-threatening junction breakdowns.